The present invention relates generally to semiconductor integrated circuit devices and manufacturing architectures of the same. More particularly, but not exclusively, the invention relates to those technologies which are adaptable for use with semiconductor integrated circuit devices having dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) modules.
Currently available DRAMs are typically designed to include an array consisting of rows and columns of memory cells disposed in a matrix form on a principal surface of a semiconductive substrate at cross points or xe2x80x9cintersectionsxe2x80x9d between a plurality of word lines and a plurality of bit lines, wherein each of the memory cells consists essentially of a capacitive element for accumulation of information and a metal insulator semiconductor field effect transistor (MISFET) for use in selecting a single memory cell, which MISFET is serially connected to the capacitive element. The memory cell selecting MISFET is formed in an active region of the semiconductor substrate which is surrounded at its periphery by an element separation or isolation region. The MISFET is generally designed to consist of a gate oxide film and a gate electrode integral with a corresponding one of the word lines, plus a pair of semiconductor active regions for use as a source and drain of the transistor. A bit line is disposed to overlie the memory cell selecting MISFET in a manner such that it is electrically connected to one of the source and drain which is commonly shared by two memory cell selection MISFETS. The information accumulation capacitive element is laid out at a location overlying the memory cell select MISFET and is electrically coupled to the remaining one of the source and drain.
A DRAM device having a memory cell structure of this type has been disclosed in Published Unexamined Japanese Patent Laid-Open No. 5-291532 and other publications. The memory cells of the DRAM as disclosed therein are designed so that word lines are increased in width or made xe2x80x9cfatxe2x80x9d in active regions (the regions in each of which a word line serves as the gate electrode of a memory cell select MISFET) and reduced in width or xe2x80x9cthinnedxe2x80x9d in the remaining regions in order to retain the required gate length when miniaturizing or xe2x80x9cdownsizingxe2x80x9d the memory cell select MISFETs, while at the same time minimizing the pitch of word lines.
In addition, the DRAM memory cells as described by the Japanese Application referred to above is arranged so that the bit lines are partly fattened to extend up to those portions overlying the active regions and a planar pattern of such active regions is designed into a gull-wing shape with part of it being bent toward the bit line side in order to achieve successful electrical conduction of more than one contact hole for use in connecting between one of the source and drain of a memory cell select MISFET and its corresponding bit line operatively associated therewith.
Regrettably the DRAM memory cells described by the above Japanese Application has the inherent problem of being unable to provide any excellent size/dimension accuracy when partly increasing the widths of word lines and bit lines or when employing the gullwing-shaped planar pattern of the active regions, due to the fact that presently available photolithography techniques suffer from difficulties in accurately achieving ultra-fine resolution of curved-line patterns and/or folded-line patterns in cases where the minimal fabricatable size becomes at or near a limit of resolution in photolithography processes as a result of further progress in microfabrication or miniaturization of such memory cells. Another problem inherent in the prior art DRAM device is that as a through-going hole for use in connecting between the lower-side electrode of an information accumulation capacitive element and the remaining one of the source and drain of its associated memory cell select MISFET is inherently disposed between one bit line and another bit line, so that partly fattening the bit lines makes it difficult to attain the intended through-hole opening margin, which leads to an inability to assure elimination of unwanted electrical short-circuiting between the lower-side electrode within a though-hole and its associative one of the bit lines.
It is therefore an object of the present invention to provide a specific technique for enabling achievement of further miniaturization of memory cells of a DRAM.
The foregoing and other objects and inventive features of this invention will become more apparent from the following description and accompanying drawings.
Some representative aspects of the present invention as disclosed herein will be explained in brief below.
(1) A semiconductor integrated circuit device incorporating the principles of the invention is arranged to have a plurality of word lines extending in a first direction on a principal surface of a semiconductive substrate, a plurality of bit lines extending in a second direction at right angles to the first direction, and an array of memory cells of a DRAM as disposed at cross points of said word lines and said bit lines, each said memory cell including a serial combination of a memory cell selecting MISFET with a gate electrode integrally formed with a corresponding one of said word lines and a capacitive element for information accumulation, wherein said plurality of word lines are arranged to linearly extend in the first direction on the principal surface of said semiconductive substrate with an identical width, and wherein a distance between adjacent ones of said word lines is less than said width.
(2) The semiconductor integrated circuit device of the invention is formed such that the distance between the adjacent ones of said gate electrodes is set at a minimal size as determined by a resolution limit of photolithography.
(3) The semiconductor integrated circuit device of the invention is formed such that said word lines and the gate electrode of said memory cell selecting MISFET integrally formed with a corresponding one of said word lines are comprised of a conductive film at least partially including a metallic film therein.
(4) The semiconductor integrated circuit device of the invention is formed such that said semiconductive substrate has an active region with said memory cell selecting MISFET formed therein and being arranged to have an island-like pattern extending in the second direction on the principal surface of said semiconductive substrate while having its periphery surrounded by an element isolation region.
(5) The semiconductor integrated circuit device of the invention is formed such that the element isolation region surrounding said active region is formed of an element separation groove having a dielectric film embedded therein as defined in the principal surface of said semiconductive substrate.
(6) The semiconductor integrated circuit device of the invention is formed such that said bit lines are formed to overlie said memory cell selecting MISFET with an insulative film laid therebetween, wherein a contact hole for electrical connection between one of a source and drain of said memory cell selecting MISFET and a corresponding one of said bit lines is formed in self-alignment with the gate electrode of said memory cell selecting MISFET.
(7) The semiconductor integrated circuit device of the invention is formed such that said information accumulation capacitive element is formed to overlie said memory cell selecting MISFET with an insulative film laid therebetween, wherein a contact hole for electrical connection between the other of the source and drain of said memory cell selecting MISFET and one electrode of said information accumulation capacitive element is formed in self-alignment with the gate electrode of said memory cell selecting MISFET.
(8) The present invention also provides a semiconductor integrated circuit device comprising a plurality of word lines extending in a first direction on a principal surface of a semiconductive substrate, a plurality of bit lines extending in a second direction at right angles to the first direction, and an array of DRAM memory cells disposed at intersections of said word lines and said bit lines, each said memory cell including a serial combination of a memory cell selecting MISFET with a gate electrode integrally formed with a corresponding one of said word lines and a capacitive element for information accumulation, wherein said bit lines linearly extend in the second direction on the principal surface of said semiconductive substrate with an identical width and wherein distance between adjacent ones of said bit lines is greater than said width.
(9) The semiconductor integrated circuit device of the invention is formed such that the width of each said bit line is equal to or less than a minimal size determinable by a resolution limit of photolithography.
(10) The semiconductor integrated circuit device of the invention is formed such that said bit lines are comprised of a conductive film at least partially containing a metallic film.
(11) The invention further provides a semiconductor integrated circuit device comprising a plurality of word lines extending in a first direction on a principal surface of a semiconductive substrate, a plurality of bit lines extending in a second direction at right angles to the first direction, and an array of DRAM memory cells disposed at intersections of said word lines and said bit lines, each said memory cell including a serial combination of a memory cell selecting MISFET with a gate electrode integrally formed with a corresponding one of said word lines and a capacitive element for information accumulation, wherein an active region with said memory cell selecting MISFET formed therein is arranged to have an island-like pattern extending in the second direction on the principal surface of said semiconductive substrate while having its periphery surrounded by an element isolation region, wherein said plurality of word lines extend along the first direction on the principal surface of said semiconductive substrate with an identical width at a distance between adjacent ones thereof, wherein a certain one of said bit lines being formed to overlie said element isolation region with a first insulative film laid therebetween extends in the second direction on the principal surface of said semiconductive substrate with an identical width at a regular distance, and wherein a first contact hole for electrical connection between one of a source and drain of said memory cell selecting MISFET formed in said active region and its associative one of said bit lines formed to overlie said element isolation region has a diameter in the first direction greater than in the second direction, with part thereof arranged to extend to overlie said element isolation region.
(12) The semiconductor integrated circuit device of the invention is formed such that said first contact hole includes a polycrystalline silicon film formed therein, wherein said polycrystalline silicon film is doped with a chosen impurity equal in conductivity type to the source and drain of said memory cell selecting MISFET.
(13) The semiconductor integrated circuit device of the invention is formed such that the corresponding one of said bit lines and said one of the source and drain of said memory cell selecting MISFET are electrically connected together via a first through-hole formed in a second insulative film sandwiched between said bit lines and said first insulative film.
(14) The semiconductor integrated circuit device of the invention is formed such that the width of said bit lines is less than a diameter of said first through-hole.
(15) The semiconductor integrated circuit device of the invention is formed such that said first contact hole has a diameter in the first direction greater than in the second direction, where a portion of the contact hole consists essentially of a first region extending to overlie said element isolation region and a second region formed beneath said first region to have a diameter in the first direction and a diameter in the second direction being substantially equal thereto, wherein said first region is formed to overlie said memory cell selecting MISFET.
(16) The semiconductor integrated circuit device of the invention is formed such that said information accumulation capacitive element is formed over said bit lines with a third insulative film laid therebetween and is electrically connected to a remaining one of the source and drain of said memory cell selecting MISFET via a second through-hole formed in said third insulative film and a second contact hole as formed in said first insulative film at a location underlying said second through-hole.
(17) The semiconductor integrated circuit device of the invention is formed such that said second contact hole includes a polycrystalline silicon film being embedded therein and doped with an impurity equal in conductivity type to the source and drain of said memory cell selecting MISFET.
(18) The semiconductor integrated circuit device of the invention is formed such that said second through-hole is disposed between neighboring ones of said bit lines and is formed in self-alignment therewith.
(19) A semiconductor integrated circuit device of the present invention comprises: an array of memory cells each including a serial combination of a MISFET for memory cell selection having a source and drain plus an insulated gate electrode and a capacitive element for data storage having first and second electrodes with a dielectric film laid therebetween; word lines including first, second and third lines extending in a first direction on a principal surface of a semiconductive substrate and each having a part used as the gate electrode of its associated memory cell selecting MISFET; and, bit lines including first and second lines disposed adjacent to each other to extend in a second direction at right angles to the first direction on the principal surface of the semiconductive substrate, wherein the first to third word lines are substantially identical in width to one another, the distance between the first word line and the second word line neighboring thereto is substantially equal to the distance between the second word line and the third word line next thereto, the distance is less than the width, the first and second bit lines are substantially the same as each other in width, which is greater than the width of these bit lines.
(20) The semiconductor integrated circuit device of this invention further comprises a first conductive layer provided between the first and second word lines for connecting the first bit line to either one of the source and drain of the memory-cell selecting MISFET and a second conductive layer laid between the second and third word lines for connecting the remaining one of the source and drain of the memory-cell selecting MISFET to the first electrode of the data storage capacitive element, wherein the aforesaid one of the source and drain of the memory-cell selecting MISFET and the first conductive layer are in self-alignment with the first word line and the second word line whereas the remaining one of the source and drain of the memory-cell selecting MISFET and the second conductive layer are self-aligned with the second word line and the third word line.
(21) The invention further provides a method of manufacturing a semiconductor integrated circuit device comprising a plurality of word lines extending in a first direction on a principal surface of a semiconductive substrate, a plurality of bit lines extending in a second direction at right angles to the first direction, and an array of DRAM memory cells disposed at intersections of said word lines and said bit lines, each said memory cell including a serial combination of a memory cell selecting MISFET with a gate electrode integrally formed with a corresponding one of said word lines and a capacitive element for information accumulation, said method comprising the steps of:
(a) forming on the principal surface of said semiconductive substrate of a first conductivity type an element isolation region and an active region of island-like pattern having its periphery surrounded by said element isolation region and extending along the second direction on the principal surface of said semiconductive substrate;
(b) patterning a first conductive film formed over the principal surface of said semiconductive substrate to form word lines extending in the first direction on the principal surface of said semiconductive substrate to have the distance between adjacent ones thereof less than the width of each said word line; and
(c) forming a source and a drain of said memory cell selecting MISFET by introducing an impurity of a second conductivity type into the principal surface of said semiconductive substrate.
(22) In the semiconductor integrated circuit device manufacturing method of the present invention, the gate electrodes are fabricated so that the distance between adjacent ones thereof is set at a minimal size determinable by a resolution limit in photolithography.
(23) The semiconductor integrated circuit device manufacturing method is arranged to include, after said step (c), the further process steps of:
(d) forming a first insulative film overlying said memory cell selecting MISFET and then forming a second insulative film overlying said first insulative film and being different in etching rate from said first insulative film;
(e) etching those portions of said second insulative film overlying the source and drain of said memory cell selecting MISFET under a condition that the etching rate of said second insulative film with respect to said first insulative film becomes greater and then etching said first insulative film overlying the source and drain of said memory cell selecting MISFET to thereby form a first contact hole overlying one of said source and drain in self-alignment with said gate electrode to have a diameter in the first direction greater than a diameter in the second direction with part of said first contact hole extending toward said element isolation region while forming a second contact hole overlying a remaining one of the source and drain in self-alignment with said gate electrode and having a diameter in the first direction which is substantially the same as its diameter in the second direction;
(f) after having embedded a conductive film in said first contact hole and said second contact hole, forming a third insulative film overlying said second insulative film and then forming a first through-hole in said third insulative film at a portion overlying a specified region extending to said element isolation region of said first contact hole; and
(g) patterning a second conductive film which is formed to overlie said third insulative film to thereby form bit lines extending along the second direction on the principal surface of said semiconductive substrate with an identical width at a distance between adjacent ones of said bit lines being greater than said width, and then electrically connecting together said first contact hole and a corresponding one of said bit lines via said first through-hole as formed in said third insulative film.
(24) The semiconductor integrated circuit device manufacturing method provides that the width of said bit lines is formed to be equal in dimension to or less than a minimal size determinable by a photolithography resolution limit.
(25) The semiconductor integrated circuit device manufacturing method is arranged to include, after said step (g), the further steps of:
(h) forming a fourth insulative film overlying said bit lines and then forming a fifth insulative film overlying said fourth insulative film at an etching rate different from that of said fourth insulative film;
(i) after having etched said fifth insulative film at a portion overlying said second contact hole under a condition that the etching rate of said fifth insulative film relative to said fourth insulative film is greater, etching said fourth insulative film at a portion overlying said second contact hole to thereby form a second through-hole overlying said second contact hole in self-alignment with a corresponding one of said bit lines; and
(j) patterning a third conductive film which is formed to overlie said fifth insulative film so as to form a lower side electrode of an information accumulation capacitive element which is electrically connected to said second contact hole via said second through-hole.